InferenceX
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ubenchX Microbenchmarks (Beta)

Low-level accelerator microbenchmarks measuring fundamental hardware characteristics.

Core memory-access profiles

Compare memory-access grouping patterns on B200 and Huawei 950PR. Each device keeps its own color scale: B200 uses clock64 cycles; 950PR uses SYS_CNT ticks. Equal colors or numbers across devices do not mean equal latency.

Huawei 950PR

Ascend 950PR_9579 · 128 MiB · Cube and Vector scalar controllers

These values are differences between memory-access profiles, not core-to-core latency, wire distance or physical coordinates. SYS_CNT ticks are not clock64 cycles or nanoseconds. Runtime IDs contain gaps; their numeric spacing is not geometric spacing.

Mean absolute difference (SYS_CNT ticks)

0113.64

All four panels use the same color scale.

Cube · One active core

cube One active core0088545461616868Physical core IDPhysical core ID

Within decoded die group: 18.55 · Between decoded die groups: 93.13 SYS_CNT ticks

Cube · Concurrent launch

cube Concurrent launch0088545461616868Physical core IDPhysical core ID

Within decoded die group: 32.37 · Between decoded die groups: 74.18 SYS_CNT ticks

Vector · One active core

vector One active core1818343472728686101101Physical core IDPhysical core ID

Within decoded die group: 18.56 · Between decoded die groups: 93.54 SYS_CNT ticks

Vector · Concurrent launch

vector Concurrent launch1818343472728686101101Physical core IDPhysical core ID

Within decoded die group: 36.51 · Between decoded die groups: 58.79 SYS_CNT ticks

Methodology

Both core types execute the same scalar pointer chase on one allocation. Six passes are averaged at each matched address, then the mean absolute difference between each pair of core profiles is computed.

Concurrent launches have no grid-wide starting barrier. Their fine structure is less repeatable than the broad grouping; these panels do not establish which cores physically share a cache.

Source data

B200 SXM: SM-SM L2 Latency Difference

Intra-GPC mean
75.6 cycles
Inter-GPC (same die) mean
82.6 cycles
Cross-die mean
269.9 cycles

Methodology

Each SM walks a linked list through L2 cache lines, recording per-hop latency with clock64(). Each cell is the mean absolute difference between two SMs’ matched-address latency profiles, not direct SM-to-SM communication latency or a physical distance.

B200 SXM: NVIDIA B200 SXM | Driver: 580.159.03 | CUDA: 13.0 | Container: sglang-20260922-582389ce-amd64.sqsh

Source: https://github.com/SemiAnalysisAI/InferenceX/pull/3881