MegaCore
Also known as MegaCore, Megacore mode, fused TPU cores
In plain English
MegaCore was the TPU v4 and v5p design that fused two physical cores into one logical accelerator sharing a single memory space.
Technical definition
MegaCore is the TPU v4 and v5p convention in which two physical TensorCores on a chip are presented to software as a single logical device with one unified HBM address space.
Engineering details
Under MegaCore, the compiler and framework saw one large device per chip, and the two cores split work behind the scenes. Ironwood drops this. Its two compute dies each run as an independent logical device with its own memory, joined by a high-bandwidth die-to-die link rather than a unified memory fabric, so JAX and TorchTPU expose two devices per chip. A TP8 configuration on Ironwood therefore spans eight logical devices on four chips.
Why it matters
The change moves coordination from hardware into software. Collectives now have an intra-chip stage across the die-to-die link and an inter-chip stage across ICI, and kernels can overlap the two. It also means per-chip figures in benchmarks aggregate two devices, which matters when comparing tokens per second per chip against a single-die GPU.
How to read it in InferenceX
The Ironwood ReduceScatter implementation on SparseCore combines contributions within each chip over the die-to-die link before exchanging partial sums across chips, which is only possible because the dies are separate devices. InferenceX reports Ironwood throughput per chip, so its 9,364 tokens per second per chip at 20 tokens per second per user covers both dies.