TensorCore (TPU)
Also known as TensorCore, TPU TensorCore, TC
In plain English
A TensorCore is the main compute block inside a TPU chip, holding the matrix units, vector units, and on-chip memory that run dense model math.
Technical definition
A TPU TensorCore is the dense compute block on a TPU die that groups one or more MXU systolic arrays, a vector processing unit, and the VMEM scratchpad those units read from and write to.
Engineering details
Ironwood carries two TensorCores per chip, one per compute die, alongside four third-generation SparseCores. The MXUs inside a TensorCore do matrix multiplies, the VPU does elementwise and reduction work, and VMEM stages operands next to both. Google TPU documentation uses the name TensorCore for this block, which is unrelated to the Tensor Cores inside NVIDIA GPU streaming multiprocessors. When a collective or gather runs on the TensorCore, it occupies cycles the MXU and VPU could otherwise spend on the model.
Why it matters
Several Ironwood optimizations move irregular work off the TensorCore and onto SparseCores so the dense units keep running. Moving ReduceScatter to SparseCore frees TensorCore execution for other operations, and moving the top-k weight gather in the ragged gather-reduce path cut TensorCore overhead from 29 microseconds to 14 in a DeepSeek-V3 microbenchmark.
How to read it in InferenceX
The TPU InferenceX preview attributes part of its 8k1k gains on Qwen3.5 397B to keeping the TensorCore free: the SparseCore expert-input rearrangement raised serving throughput 12% over the original kernels, and a VMEM-derived threshold keeps small collectives on the TensorCore when SparseCore offload would be slower.