Head-to-head AI inference benchmark comparison of B300 (NVIDIA Blackwell) and Vera Rubin NVL72 (NVIDIA Vera Rubin) on MiniMax M3 428B. Latency, throughput, and cost across LLM workloads. Use the chart controls below to switch sequences, precisions, and metrics — same interactions as the main inference chart.
AgentX replays real coding-agent sessions rather than fixed-length prompts, so context grows turn over turn and most of each request is served from cache instead of being recomputed. That turns the comparison into a systems question: KV transfer between nodes, prefix-aware routing, and cache capacity all move the curve alongside raw chip throughput. Fixed-sequence workloads stay the clean baseline for kernel and silicon performance, so the two scenarios answer different questions about the same hardware. Learn more about AgentX →
Near the low end of the 102–389 tok/s/user interactivity band, at 173 tok/s/user on MiniMax M3 428B: B300 runs 33987 tok/s/chip at $0.02/M tokens, Vera Rubin NVL72 runs 150058 at $0.01/M. Vera Rubin NVL72 is 176% cheaper per token; Vera Rubin NVL72 delivers 342% more tok/s/chip.
Setting 245 tok/s/user as the target on MiniMax M3 428B, B300 produces 20285 tok/s/chip ($0.03 per million tokens) and Vera Rubin NVL72 produces 113350 ($0.01). Vera Rubin NVL72 is 250% cheaper per token; Vera Rubin NVL72 delivers 459% more tok/s/chip.
At 317 tok/s/user interactivity on MiniMax M3 428B, B300 delivers 7521 tok/s/chip at $0.08 per million tokens; Vera Rubin NVL72 delivers 75112 tok/s/chip at $0.01. Vera Rubin NVL72 is 525% cheaper per token; Vera Rubin NVL72 delivers 899% more tok/s/chip at this point. (Numbers reflect the default agentic-traces · fp4 selection for this URL — table and chart below update if you change sequence, precision, or model in the controls.)
| Metric | Interactivity (tok/s/user) | Interactivity (tok/s/user) | Interactivity (tok/s/user) |
|---|---|---|---|
| Throughput (tok/s/chip) | B300:33986.8Vera Rubin NVL72:150057.6 | B300:20284.9Vera Rubin NVL72:113349.8 | B300:7521.5Vera Rubin NVL72:75112.0 |
| Cost ($/M tok) | B300:$0.018Vera Rubin NVL72:$0.007 | B300:$0.031Vera Rubin NVL72:$0.009 | B300:$0.083Vera Rubin NVL72:$0.013 |
| tok/s/MW | B300:17887800Vera Rubin NVL72:45471994 | B300:10676285Vera Rubin NVL72:34348429 | B300:3958681Vera Rubin NVL72:22761216 |
| Concurrency | B300:~20Vera Rubin NVL72:~45 | B300:~14Vera Rubin NVL72:~33 | B300:~3Vera Rubin NVL72:~21 |
Agentic inference metrics from the AgentX scenario and fixed-sequence inference metrics across models, hardware configurations, and serving parameters.
TCO $/chip/hr:
Source: SemiAnalysis Market July 2026 Pricing Surveys & AI Cloud TCO Model
Note: Disaggregated inference configurations (e.g., MoRI SGLang, Dynamo TRTLLM) calculate cost per million tokens per decode chip or per prefill chip, rather than per total chip count. This makes direct token cost comparison with aggregated configs not an apples-to-apples comparison.
Note: Disaggregated inference configurations (e.g., MoRI SGLang, Dynamo TRTLLM) calculate input throughput per decode chip or per prefill chip, rather than per total chip count. This makes direct input throughput comparison with aggregated configs not an apples-to-apples comparison.
Note: Disaggregated inference configurations (e.g., MoRI SGLang, Dynamo TRTLLM) calculate output throughput per decode chip or per prefill chip, rather than per total chip count. This makes direct output throughput comparison with aggregated configs not an apples-to-apples comparison.
Note: Disaggregated inference configurations (e.g., MoRI SGLang, Dynamo TRTLLM) calculate power per decode chip or per prefill chip, rather than per total chip count. This makes direct power comparison with aggregated configs not an apples-to-apples comparison.
Note: Disaggregated inference configurations (e.g., MoRI SGLang, Dynamo TRTLLM) calculate Joules per decode chip or per prefill chip, rather than per total chip count. This makes direct Joules per token comparison with aggregated configs not an apples-to-apples comparison.
Matching measurements exist, but their chip series are hidden.
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