Hardware
Chip binning
In plain English
Sorting manufactured chips or memory components into configurations based on tested functionality, power, and performance.
Technical definition
Binning classifies manufactured components according to which resources work and which operating targets they meet, rather than assuming every die is identical.
Engineering details
Defects can disable resources, while variation in frequency, voltage, power, or memory capability can limit otherwise functional parts. A vendor can create product configurations by selecting and pairing components or disabling resources. The resulting SKU does not reveal every physical detail of an individual device.
Why it matters
Nominally similar systems can differ in enabled resources and locality. Benchmark reports need actual device configuration and operating conditions before attributing variation entirely to software.
How to read it in InferenceX
The Huawei port discusses compute and memory configurations; the Blackwell port examines enabled SM groupings. These are architectural observations, not direct measurements of manufacturing yield rates.
See the concept in real benchmarks
All articlesThe Huawei-DeepSeek Symbiosis
Ascend 950PR architecture and microbenchmarks, DeepSeek’s Ascend software stack, and the DeepSeek-V4.1-Flash execution profile.
Dissecting Nvidia Blackwell - Tensor Cores, PTX Instructions, SASS, Floorsweep, Yield
Blackwell SM100 microbenchmarks of PTX and SASS instructions, tensor-core shapes, memory copies, cluster scheduling, and floorsweeping.