Boardfly
Also known as Boardfly topology, TPU 8i network, TPUv8i Boardfly
In plain English
Boardfly is the new flatter network in Google’s inference-only TPU 8i that cuts the number of hops between chips roughly in half compared with a torus.
Technical definition
Boardfly is the high-radix, hierarchical interconnect topology of TPU 8i that replaces the nearest-neighbor 3D torus, named after the dragonfly family of supercomputer networks.
Engineering details
TPU 8t, the training chip, keeps the 3D torus. TPU 8i, the inference chip, switches to Boardfly, a fabric of high-radix switches rather than a mesh of direct neighbor links. At comparable scale in the 1,024 to 1,152 chip range, network diameter falls from roughly 16 hops to about 7. TPU 8i pairs this with 19.2 Tb/s of ICI bandwidth, double the prior generation, and 384 MB of on-chip SRAM, three times the prior generation, sized to hold the KV cache of reasoning and agentic models on chip. It also brings native FP4 compute, which Ironwood lacks.
Why it matters
Fewer hops mean lower tail latency on collectives, which matters when tokens route across MoE layers or when a multi-turn agent session compounds every extra hop into user-visible latency. Boardfly also changes networking attachment capex per chip. This is the first time Google has split training and inference into separate architectures.
How to read it in InferenceX
SemiAnalysis expects TPUv8i Boardfly to be competitive with Rubin NVL72. When TPUv8i lands on InferenceX and AgentX, the comparison against NVIDIA moves from FP8 versus FP8 to FP4 versus FP4, removing the quality asymmetry in the current Ironwood results.