Head-to-head AI inference benchmark comparison of H100 (NVIDIA Hopper) and Vera Rubin NVL72 (NVIDIA Vera Rubin) on MiniMax M3 428B. Latency, throughput, and cost across LLM workloads. Use the chart controls below to switch sequences, precisions, and metrics β same interactions as the main inference chart.
AgentX replays real coding-agent sessions rather than fixed-length prompts, so context grows turn over turn and most of each request is served from cache instead of being recomputed. That turns the comparison into a systems question: KV transfer between nodes, prefix-aware routing, and cache capacity all move the curve alongside raw chip throughput. Fixed-sequence workloads stay the clean baseline for kernel and silicon performance, so the two scenarios answer different questions about the same hardware. Learn more about AgentX β
At 7 tok/s/user on MiniMax M3 428B, H100 delivers 780 tok/s/chip at $0.42 per million tokens; Vera Rubin NVL72 hasn't been benchmarked at this target.
H100 hits 659 tok/s/chip for $0.49 per million tokens at 11 tok/s/user on MiniMax M3 428B. No Vera Rubin NVL72 data at this operating point.
H100: 637 tok/s/chip, $0.51 per million tokens at 15 tok/s/user on MiniMax M3 428B. Vera Rubin NVL72 is unmeasured here. (Numbers reflect the default agentic-traces Β· fp8 selection for this URL β table and chart below update if you change sequence, precision, or model in the controls.)
| Metric | Interactivity (tok/s/user) | Interactivity (tok/s/user) | Interactivity (tok/s/user) |
|---|---|---|---|
| Throughput (tok/s/chip) | H100:780.2Vera Rubin NVL72:β | H100:659.0Vera Rubin NVL72:β | H100:637.0Vera Rubin NVL72:β |
| Cost ($/M tok) | H100:$0.417Vera Rubin NVL72:β | H100:$0.493Vera Rubin NVL72:β | H100:$0.510Vera Rubin NVL72:β |
| tok/s/MW | H100:569485Vera Rubin NVL72:β | H100:481042Vera Rubin NVL72:β | H100:464987Vera Rubin NVL72:β |
| Concurrency | H100:~6Vera Rubin NVL72:β | H100:~3Vera Rubin NVL72:β | H100:~1Vera Rubin NVL72:β |
Agentic inference metrics from the AgentX scenario and fixed-sequence inference metrics across models, hardware configurations, and serving parameters.
TCO $/chip/hr:
Source: SemiAnalysis Market July 2026 Pricing Surveys & AI Cloud TCO Model
Note: Disaggregated inference configurations (e.g., MoRI SGLang, Dynamo TRTLLM) calculate cost per million tokens per decode chip or per prefill chip, rather than per total chip count. This makes direct token cost comparison with aggregated configs not an apples-to-apples comparison.
Note: Disaggregated inference configurations (e.g., MoRI SGLang, Dynamo TRTLLM) calculate input throughput per decode chip or per prefill chip, rather than per total chip count. This makes direct input throughput comparison with aggregated configs not an apples-to-apples comparison.
Note: Disaggregated inference configurations (e.g., MoRI SGLang, Dynamo TRTLLM) calculate output throughput per decode chip or per prefill chip, rather than per total chip count. This makes direct output throughput comparison with aggregated configs not an apples-to-apples comparison.
Note: Disaggregated inference configurations (e.g., MoRI SGLang, Dynamo TRTLLM) calculate power per decode chip or per prefill chip, rather than per total chip count. This makes direct power comparison with aggregated configs not an apples-to-apples comparison.
Note: Disaggregated inference configurations (e.g., MoRI SGLang, Dynamo TRTLLM) calculate Joules per decode chip or per prefill chip, rather than per total chip count. This makes direct Joules per token comparison with aggregated configs not an apples-to-apples comparison.
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