Head-to-head AI inference benchmark comparison of B300 (NVIDIA Blackwell) and Vera Rubin NVL72 (NVIDIA Vera Rubin) on MiniMax M3 428B. Latency, throughput, and cost across LLM workloads. Use the chart controls below to switch sequences, precisions, and metrics β same interactions as the main inference chart.
AgentX replays real coding-agent sessions rather than fixed-length prompts, so context grows turn over turn and most of each request is served from cache instead of being recomputed. That turns the comparison into a systems question: KV transfer between nodes, prefix-aware routing, and cache capacity all move the curve alongside raw chip throughput. Fixed-sequence workloads stay the clean baseline for kernel and silicon performance, so the two scenarios answer different questions about the same hardware. Learn more about AgentX β
Near the low end of the 87β390 tok/s/user interactivity band, at 162 tok/s/user on MiniMax M3 428B: B300 runs 35980 tok/s/chip at $0.02/M tokens, Vera Rubin NVL72 runs 109245 at $0.01/M. Vera Rubin NVL72 is 90% cheaper per token; Vera Rubin NVL72 delivers 204% more tok/s/chip.
Setting 238 tok/s/user as the target on MiniMax M3 428B, B300 produces 20628 tok/s/chip ($0.03 per million tokens) and Vera Rubin NVL72 produces 74624 ($0.01). Vera Rubin NVL72 is 126% cheaper per token; Vera Rubin NVL72 delivers 262% more tok/s/chip.
At 315 tok/s/user interactivity on MiniMax M3 428B, B300 delivers 7146 tok/s/chip at $0.09 per million tokens; Vera Rubin NVL72 delivers 50690 tok/s/chip at $0.02. Vera Rubin NVL72 is 344% cheaper per token; Vera Rubin NVL72 delivers 609% more tok/s/chip at this point. (Numbers reflect the default agentic-traces Β· fp4 selection for this URL β table and chart below update if you change sequence, precision, or model in the controls.)
| Metric | Interactivity (tok/s/user) | Interactivity (tok/s/user) | Interactivity (tok/s/user) |
|---|---|---|---|
| Throughput (tok/s/chip) | B300:35980.2Vera Rubin NVL72:109244.8 | B300:20628.1Vera Rubin NVL72:74624.5 | B300:7145.5Vera Rubin NVL72:50690.2 |
| Cost ($/M tok) | B300:$0.017Vera Rubin NVL72:$0.009 | B300:$0.030Vera Rubin NVL72:$0.013 | B300:$0.088Vera Rubin NVL72:$0.020 |
| tok/s/MW | B300:18936928Vera Rubin NVL72:33104490 | B300:10856871Vera Rubin NVL72:22613478 | B300:3760796Vera Rubin NVL72:15360667 |
| Concurrency | B300:~21Vera Rubin NVL72:~37 | B300:~14Vera Rubin NVL72:~20 | B300:~2Vera Rubin NVL72:~28 |
Agentic inference metrics from the AgentX scenario and fixed-sequence inference metrics across models, hardware configurations, and serving parameters.
TCO $/chip/hr:
Source: SemiAnalysis Market July 2026 Pricing Surveys & AI Cloud TCO Model
Note: Disaggregated inference configurations (e.g., MoRI SGLang, Dynamo TRTLLM) calculate cost per million tokens per decode chip or per prefill chip, rather than per total chip count. This makes direct token cost comparison with aggregated configs not an apples-to-apples comparison.
Note: Disaggregated inference configurations (e.g., MoRI SGLang, Dynamo TRTLLM) calculate input throughput per decode chip or per prefill chip, rather than per total chip count. This makes direct input throughput comparison with aggregated configs not an apples-to-apples comparison.
Note: Disaggregated inference configurations (e.g., MoRI SGLang, Dynamo TRTLLM) calculate output throughput per decode chip or per prefill chip, rather than per total chip count. This makes direct output throughput comparison with aggregated configs not an apples-to-apples comparison.
Note: Disaggregated inference configurations (e.g., MoRI SGLang, Dynamo TRTLLM) calculate power per decode chip or per prefill chip, rather than per total chip count. This makes direct power comparison with aggregated configs not an apples-to-apples comparison.
Note: Disaggregated inference configurations (e.g., MoRI SGLang, Dynamo TRTLLM) calculate Joules per decode chip or per prefill chip, rather than per total chip count. This makes direct Joules per token comparison with aggregated configs not an apples-to-apples comparison.
Matching measurements exist, but their chip series are hidden.
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